Principal Engineer , Memory Design

Overview

Principal Engineer for memory design, focused on DRAM memory array and related circuit design, optimization, verification, and layout oversight.

What you'll do

• Assist with overall design, layout, and optimization of DRAM memory array, peripheral logic, and analog circuits.
• Use AI-based tools, agentic workflows, and automation frameworks for schematic optimization and design-space exploration.
• Perform parasitic analysis, sensitivity studies, and corner coverage.
• Improve debug efficiency across simulation and silicon learning loops.
• Oversee memory layout including floor-planning, placement, and routing.
• Conduct circuit-level verification for functional, timing, power, and reliability using specified simulators/tools.

What you'll need

• Master’s degree in electrical or computer engineering.
• 4-8 years of experience in memory design.
• Strong fundamentals in CMOS circuit design, device physics, and memory operation.
• Experience with SPICE-based simulation and parasitic extraction.

Details

• Location: Hyderabad, Telangana, India.