Senior Staff Engineer

Overview

Senior Staff Engineer responsible for independently owning IP design verification and contributing to subsystem and SoC verification execution.

What you'll do

• Own IP design verification independently.
• Create verification test plans.
• Build testbenches using standard design verification methodology.
• Develop coverage, regression, and simulation infrastructure.
• Collaborate with cross-functional teams across multiple locations.
• Lead IP verification projects and provide technical guidance.
• Debug verification issues and support DV sign-offs.

What you'll need

• 7–10 years of experience.
• B.Tech, B.E, M.Tech, or M.E qualification.
• Experience developing testbenches for IP, subsystems, or SoCs.
• Hands-on experience with SoC, subsystem, or IP design verification.
• Strong experience with UVM, SystemVerilog, CDV, and MDV.
• Expertise in at least one of AXI, PCIe, or UCIe.
• Understanding of SoC architecture and verification methodologies.

Nice to have

• Experience with hybrid SystemVerilog, SystemC, and Python testbenches.
• Experience with SystemC-based reference-model test-vector or stimulus verification.
• Protocol experience in AXI, PCIe, or UCIe.

Details

• Location: Bangalore, India.