Silicon Design Verification Engineer

Overview

Validate Intel client SOC designs by planning and executing tests for DFx features and complex microarchitecture blocks, working from specs and RTL, and supporting silicon debug.

What you'll do

• Validate DFx features such as Scan, SBFT, TAP, Arrays, Fuse and MBIST using simulation and emulation.
• Create plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
• Learn the architecture and microarchitecture by debugging failures to the root cause.
• Develop and utilize DFT and validation tools and/or methodologies to implement validation plans and ensure a solid design.
• Participate in debug of failures on silicon and develop new testing strategies to detect these failures on RTL models.
• Engage with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution.
• Develop tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible.
• Develop debugging tools and software.

What you'll need

• Either a BS + 5 years' experience or MS + 3 years' experience in Computer Science, Computer Engineering or Electrical Engineering.
• Minimum 3 years' experience with reading and interpreting technical specs and Register Transfer Level (RTL) code.
• Minimum 3 years' experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM.
• Minimum 3 years' experience with writing validation plans and software to implement those validation plans.
• Minimum 1 year experience with UNIX or Linux.

Nice to have

• Minimum 1 year experience with computer architecture.
• Minimum 1 year experience with IA-32 assembly and/or Verilog programming experience.
• Minimum 2 years' experience with validation or testing experience, especially in a silicon design team.
• 3+ years' experience with industry standards such as Scan, JTAG, BScan.
• Experience in Coherency.

Details

• Experienced hire; Shift 1 (India).
• Location: India, Bangalore.
• Hybrid work model: split time between on-site at assigned Intel site and off-site.