SR ENGINEER, DDEG Design Methodology

Overview

SR Engineer for DDEG Design Methodology focused on verification and end-to-end analysis of full chip gate-level custom DRAM designs, including low power and power management aspects.

What you'll do

• Leverage AI-based tools, agentic workflows, and automation to accelerate verification cycle time.
• Assist in developing test-case/testbench components for DRAM design verification.
• Improve debug efficiency across simulation and silicon learning loops.
• Simulate, analyze, and debug pre-silicon block level and full chip designs.
• Develop test cases/stimulus to increase functional coverage for DRAM and emerging memory architectures.
• Develop and maintain test benches/test vectors and run regressions for coverage analysis and improvements.
• Contribute to verification methodology and verification environments for advanced DRAM and emerging memory products.

What you'll need

• Experience in SystemVerilog, including PLI coding.
• UVM test bench experience.
• Experience in DRAM, SRAM, or other memory-related fields.
• Proficiency with SPICE and/or Verilog simulations.
• Good understanding of digital/mixed signal circuits and digital/mixed signal verification.
• Tool familiarity including Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice.

Details

• Location: Hyderabad - Phoenix Aquila, India.