SR ENGINEER, DDEG Design Methodology

Overview

SR Engineer for DDEG Design Methodology, owning verification and end-to-end analysis of full chip gate-level custom DRAM/memory designs with low-power and power management focus.

What you'll do

• Leverage AI-based tools, agentic workflows, and automation frameworks to accelerate verification cycle time.
• Develop and improve test cases/test benches and run regressions for coverage analysis.
• Simulate, analyze, and debug pre-silicon block-level and full-chip designs.
• Improve debug efficiency across simulation and silicon learning loops.
• Validate AI outputs by reviewing assumptions, aligning with specs/standards, and cross-checking with simulations/waveforms/coverage.
• Collaborate internationally to develop new verification flows and verification methodologies/environments.

What you'll need

• Experience in SystemVerilog and UVM test bench work for verification.
• Experience in DRAM, SRAM, or other memory-related fields.
• Proficiency with SPICE and/or Verilog simulations.
• Experience in digital/mixed-signal verification and familiarity with tools (Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice).
• Experience in writing Verilog and Real Number Models (SV and gate-level context).
• Good communication and debugging skills and ability to work in a team.

Details

• Location: Hyderabad, Telangana, India.