Sr. Memory Layout Design Engineer

Overview

Senior Memory Layout Design Engineer responsible for memory layout design, floor-planning and physical verification for submicron CMOS processes, leading layout scheduling and deliverables and mentoring junior engineers.

What you'll do

• Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
• Manage scheduling, timelines, and layout floor-planning.
• Take responsibility for start-to-end deliverables with quality within the planned schedule.
• Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.
• Help with layout scripting and automation.
• Plan signal and power routing based on layout guidelines and memory architecture and RC requirements.
• Lead, train junior engineers, and manage projects effectively.
• Lead new technology reviews to document layout methodologies, flows, and guidelines.

What you'll need

• Minimum 8 years of experience with strong layout knowledge.
• Bachelor's degree required.
• Proficiency in Cadence tools (Virtuoso layout, Layout XL, Cadence schematic capture) and verification tools (Calibre and Hercules).
• Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).
• Experience in digital layout (standard cell, memory, I/O).
• Strong experience in memory layout design and physical verification (LVS, DRC, ERC, antenna, electromigration) in CMOS processes.
• Experience with Cadence layout tools (Virtuoso XL, VXL, or EXL) and Calibre verification tools.
• Proficiency in floor-planning, hierarchy layout, and chip integration.
• Understanding of memory architecture and RC requirements, with the ability to plan signal and power based on layout guidelines.
• Knowledge of AI, automation in layout, script programming and SKILL programming.
• Ability to lead, train junior engineers, and manage projects effectively.
• Good knowledge of memory layout topology.
• Self-reliant, able to work both independently and collaboratively.

Nice to have

• Analog layout experience.
• Experience with memory compilers.

Details

• Location: Bangalore Electronic City, India.