Staff Engineer, RTL Design

Overview

Staff Engineer for RTL design, owning the overall logic design of the on-chip memory controller for new memory products.

What you'll do

• Own the overall logic design of the on-chip memory controller, including all optimizations and pathfinding.
• Meet performance, area and power targets.
• Interpret device and system specifications to produce required functionality.
• Participate in new circuit conception and design as needed.
• Define and build design architecture spec documents for new features.
• Architect, design and integrate complex RTL blocks for sophisticated memory products, driving functionality from specification through verification and design closure.
• Develop and optimize synthesis and timing constraints, perform STA, and resolve timing challenges to meet performance, power and area objectives.
• Carry out back-end implementation activities including APR, timing closure, physical signoff readiness, and functional/timing ECO execution.
• Maintain technical expertise and provide training.
• Define best known design and verification practices and communicate them to the entire department.
• Prepare detailed documentation as required.
• Participate in recruiting and interviewing new candidates.
• Build new hire ramp-up plans.
• Engage in continuing education and competitor analysis.
• Perform RTL and synthesized netlist (gate level) verification at block, subsystem and fullchip level.
• Facilitate netlist bring-up to achieve basic functionality.
• Deliver design simulation including post-layout.
• Create verification plans for new and existing features and check expected behavior in Verilog.
• Collaborate with Product Engineering on validation plans and review silicon results.
• Assist in silicon design validation, reticle experiments, qual and tape-out revisions as needed.
• Contribute to cross-group communication to work towards standardization and group success.
• Work with Device, System, Probe, Test, CAD, Field Application Engineers and Product Engineering groups to ensure accurate manufacturability of product.
• Proactively solicit mentorship from various groups (e.g. standard cell development, simulation, voltage).
• Improve process efficiency and quality by leveraging AI flows.
• Leverage artificial intelligence for code generation and verification flows.

Details

• Location: Hyderabad, Telangana, India.