Staff Engineer – STA Methodology/CAD

Overview

Staff Engineer role focused on developing, deploying, and enhancing Static Timing Analysis (STA) methodologies for complex SoCs.

What you'll do

• Define, develop, and improve STA methodologies for block, subsystem, and full-chip designs.
• Drive timing signoff flows including MMMC analysis, constraint validation, ECO methodologies, and correlation strategies.
• Build automation and infrastructure for timing analysis using Tcl/Python/Perl.
• Own methodology development for timing closure, reporting, constraint management, and signoff quality metrics.
• Collaborate with RTL, Synthesis, Physical Design, DFT, and CAD teams for timing convergence.
• Adopt advanced timing techniques including SOCV/AOCV, hierarchical STA, and signoff optimization flows.

What you'll need

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
• 7+ years of experience in STA, Timing Signoff, Timing Methodology, or CAD/EDA methodology development.
• Strong understanding of Static Timing Analysis (STA) and MMMC timing signoff.
• Strong understanding of timing constraints (SDC) and Setup/Hold closure methodologies.
• Expertise in SOCV/AOCV derates and ECO and timing convergence techniques.
• Experience with Synopsys PrimeTime or Cadence Tempus.
• Strong scripting skills in Tcl and Python.