Staff Engineer – Synthesized Model IP Design

Overview

Staff Engineer to develop and deliver synthesized IP models for emulation and FPGA prototyping platforms.

What you'll do

• Lead design and development of synthesizable IP models for emulation and FPGA prototyping.
• Contribute to architecture and micro-architecture definition and implementation strategies.
• Develop and optimize RTL using Verilog/SystemVerilog for functionality, performance, area, and timing closure.
• Develop and maintain C/C++ reference models aligned with RTL implementations.
• Drive IP integration, debug, validation, and bring-up across simulation, emulation, and FPGA environments.
• Prepare project plans, estimate schedules, identify technical risks, and drive execution to milestones.
• Mentor 2-4 engineers through technical guidance and code reviews.

What you'll need

• 10+ years of experience in ASIC/SoC/FPGA/RTL design or emulation/prototyping domains.
• Strong expertise in synthesizable model development and Verilog/SystemVerilog RTL design.
• Proficiency in C/C++ for reference model development and validation frameworks.
• Experience contributing to architecture/micro-architecture discussions and translating specs to RTL.
• Good understanding of AXI/AHB/APB protocols, CDC, reset architecture, power management, and system-level integration.
• Experience with Git and CI/CD workflows, plus scripting using Python, Tcl, Perl, or Shell.
• Hands-on experience with Xilinx FPGA design/prototyping flows (AMD/Xilinx UltraScale+ and Versal).

Details

• Location: Bangalore, India.
• Mentor: 2-4 engineers.