Staff Engineer: Verification of Power Management

Overview

Lead verification and optimization of RISC-V Low Power Profiles, including UPF, and drive quality closure at CPU and block levels.

What you'll do

• Lead the verification and optimization of diverse RISC-V Low Power Profiles, including UPF.
• Drive and achieve quality closure targets at both the CPU and block levels.
• Collaborate closely with microarchitecture and RTL design teams to optimize complex Power flows.
• Provide technical leadership and mentorship to junior team members to foster team growth and enrichment.
• Actively participate in the test planning and execution phases for new architecture and design features.

What you'll need

• 9+ years of experience in low power, power aware or power management.
• Hands-on UVM Test Bench development experience.
• Experience with power simulation on VCS and UPF.
• Experience with script writing in Python, Perl or Tcl.
• Experience with power impact at architecture, logic design, and circuit levels.
• Excellent problem solving skill and ability to work in a dynamic and diverse environment.
• A minimum of bachelor's or master's degree, or equivalent, in Electrical & Electronic Engineering, Electrical & Communication Engineering or VLSI, with consistently good academics.

Nice to have

• Experience in core uArch.
• Experience in leading effort and driving multiple projects.

Details

• Location: Bengaluru, Karnataka, India.
• Requires a successful background and reference checks and satisfactory proof of right to work in India.
• Offer contingent on verification of authorization for access to export-controlled technology under applicable export control laws, or ability to obtain any necessary export license(s) or other approvals.