Tech Lead, Asic DV

Overview

Lead design verification of PCIe and CXL based SoC and silicon designs, from verification planning through coverage closure.

What you'll do

• Develop and execute block-level and system-level verification plans.
• Write and execute test sequences and collect and close coverage.
• Collaborate with RTL designers to debug failures and refine verification processes.
• Utilize coding and protocol expertise to contribute to functional verification.
• Develop user-controlled random constraints in transaction-based verification methodologies.
• Write assertions, cover properties, and analyze coverage data.
• Create VIP abstraction layers for sequences to simplify and scale verification deployments.

What you'll need

• Minimum of 6 years' experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
• Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor's degree required).
• Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction.
• Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.
• Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.
• Ability to independently develop test plans and sequences in UVM to generate stimuli.
• Experience writing assertions, cover properties, and analyzing coverage data.
• Developing VIP abstraction layers for sequences to simplify and scale verification deployments.

Nice to have

• Master's degree in Electrical Engineering or Computer Engineering.
• Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC.
• Experience with buffering and queuing with QoS on complex NOC-based SoCs.
• Analyzing performance at the system level on switching fabrics.

Details

• Location: Bengaluru, Karnataka, India.