Tech Lead– Verification Methodology/CAD

Overview

Tech Lead for verification methodology, CAD, and automation focused on building verification infrastructure and reusable methodologies across IP and SoC verification teams.

What you'll do

• Own and drive verification methodology and infrastructure across projects.
• Develop scalable frameworks for simulation, regression, coverage, debug, and verification signoff.
• Build and maintain verification CAD/automation flows.
• Automate test generation, compilation, regression execution, result collection, and reporting.
• Develop infrastructure for large-scale UVM/SystemVerilog verification environments.
• Integrate multiple verification tools into common workflows and build dashboards/metrics.

What you'll need

• 6–12 years of experience.
• Strong experience in verification methodology, CAD, and automation.
• Programming/scripting skills in Python, Tcl, Perl, and Shell (preferably C/C++).
• Strong understanding of SystemVerilog/UVM.
• Experience with simulation tools such as VCS, Xcelium, Questa, or equivalents.
• Strong Linux/Unix environment experience.
• Strong knowledge of coverage collection and analysis.

Details

• Location: Bengaluru, Karnataka, India.