Which of the following is an unsigned 2-state data type?

Which of the following is a legal Verilog identifier?

Which of the following is not a type of Verilog net datatype?

Which of the following is not a Verilog keyword?

reg [3:0] num;

reg [7:0] val = 8'b10110100;

num = val[7-:4];

The value stored in num is:

Which of the following is not a level of abstraction in Verilog?

In the always @() Concurrent Block specifier, the parenthesis contains the _________ list.

Which type of shift operator does the following represent?

" >>> "

The purpose of the $stop system task is:

In System Verilog, what is Instantiation?