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System-verilog Questions Set 17:

Quiz Mode

For which data types can arrays be used in Verilog?

reg

time

integer

all of the above

Solution:

The _________ statement is a fundamental statement in Verilog.

Conditional

Loop

Assignment

Library

Solution:

Which of the following comprises the white space in Verilog?

Blank space

Tab space

New lines

All of the above

Solution:

What is the output of the following Verilog code?

a=20, b=22, c=42

a=20, b=2, c=42

a=20, b=2, c=22

a=20, b=22, c=22

Solution:

The two types of Signal Identifiers in Verilog are:

Primitives and Instances

Input and Output Ports

Modules and Synthesis

Wire and Registers

Solution:

What is the value of the 4-bit register `s` after the code below is executed?

`module array();`

  `reg [3:0] s;`

  `initial begin`

  `s = 5'b11101;`

  `$display("%0b" , s);`

  `end`

`endmodule`

Error

11101

1101

101

Solution:

What is the output of the following Verilog code?

`module packed_array;`

`initial begin`

`bit [63:0][7:0]arr_p;`

`$display("Size of packed array is %0d",$size(arr_p));`

`end`

`endmodule`

512

None of the above

Solution:

The keyword #ifndef simply tells the compiler to include the piece of code until the next `#else` or `#endif` if the given macro called `FLAG` is not defined using a `#define` directive.

#ifdef

#ifndef

#def

#ndef

Solution:

Among the following, the wrong way of commenting is _____

reg [3:0]b; /* b is a //4 bit register*/

reg [3:0]b; /* b is a /*4 bit*/ register */

reg [3:0]b ; /* b is a 4 bit register*/

reg [3:0]b; // b is a 4 bit register

Solution:

The statement claims that the reduction of NAND, NOR, and XNOR are performed using the reduction operator in Verilog Programming. Comment on the accuracy of this statement.

False. None of the reductions can be performed using the reduction operator.

False. Only the reduction of NAND can be performed using the reduction operator.

False. Only the reduction of NOR can be performed using the reduction operator.

False. Only the reduction of XNOR can be performed using the reduction operator.

System-verilog Questions Set 17:

For which data types can arrays be used in Verilog?

Solution:

The _________ statement is a fundamental statement in Verilog.

Solution:

Which of the following comprises the white space in Verilog?

Solution:

What is the output of the following Verilog code?

Solution:

The two types of Signal Identifiers in Verilog are:

Solution:

What is the value of the 4-bit register `s` after the code below is executed?

`module array();`

  `reg [3:0] s;`

  `initial begin`

  `s = 5'b11101;`

  `$display("%0b" , s);`

  `end`

`endmodule`

Solution:

What is the output of the following Verilog code?

`module packed_array;`

`initial begin`

`bit [63:0][7:0]arr_p;`

`$display("Size of packed array is %0d",$size(arr_p));`

`end`

`endmodule`

Solution:

The keyword #ifndef simply tells the compiler to include the piece of code until the next `#else` or `#endif` if the given macro called `FLAG` is not defined using a `#define` directive.

Solution:

Among the following, the wrong way of commenting is _____

Solution:

The statement claims that the reduction of NAND, NOR, and XNOR are performed using the reduction operator in Verilog Programming. Comment on the accuracy of this statement.

Solution:

Related Question Sets:

Related Topics:

System-verilog Questions Set 17:

For which data types can arrays be used in Verilog?

Solution:

The _________ statement is a fundamental statement in Verilog.

Solution:

Which of the following comprises the white space in Verilog?

Solution:

What is the output of the following Verilog code?

Solution:

The two types of Signal Identifiers in Verilog are:

Solution:

What is the value of the 4-bit register s after the code below is executed? module array(); reg [3:0] s; initial begin s = 5'b11101; $display("%0b" , s); end endmodule

Solution:

What is the output of the following Verilog code? module packed_array; initial begin bit [63:0][7:0]arr_p; $display("Size of packed array is %0d",$size(arr_p)); end endmodule

Solution:

The keyword #ifndef simply tells the compiler to include the piece of code until the next #else or #endif if the given macro called FLAG is not defined using a #define directive.

Solution:

Among the following, the wrong way of commenting is _____

Solution:

The statement claims that the reduction of NAND, NOR, and XNOR are performed using the reduction operator in Verilog Programming. Comment on the accuracy of this statement.

Solution:

Related Question Sets:

Related Topics:

What is the value of the 4-bit register `s` after the code below is executed?

`module array();`

`reg [3:0] s;`

`initial begin`

`s = 5'b11101;`

`$display("%0b" , s);`

`end`

`endmodule`

What is the output of the following Verilog code?

`module packed_array;`

`initial begin`

`bit [63:0][7:0]arr_p;`

`$display("Size of packed array is %0d",$size(arr_p));`

`end`

`endmodule`

The keyword #ifndef simply tells the compiler to include the piece of code until the next `#else` or `#endif` if the given macro called `FLAG` is not defined using a `#define` directive.