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System-verilog Questions Set 4:

Quiz Mode

Which of the following are the 'equality' operators in Verilog?

===

!==

All of the above

Solution:

In the code given above, the task is used to convert the units of _________.

speed

temperature

angle

distance

Solution:

Which type of ROM can be easily erased even when positioned inside the computer?

Flash ROM

EEPROM

EPROM

Mask ROM

Solution:

Which of the following cannot be used while implementing a program using tasks and functions?

registers

time variables

integers

wires

Solution:

The Verilog code given below describes the function of a D-Latch using behavioral description.

D-Latch, Behavioral

SR-Latch, Structural

SR-Latch, Behavioral

D-Latch, Structural

Solution:

Which of the following variable declaration is correct in Verilog?

Given that the variable is a memory “Mem” of size 64x16

reg [15:0] Mem[0:63];

reg [63:0] Mem[0:16];

wire [15:0] Mem[0:63];

reg [15:0][0:63]Mem;

Solution:

Which of the following statements about blocking assignment statements is false?

It will not cause a degradation in simulator performance.

It can potentially cause race conditions.

The final result is not dependent on the order in which assignments are evaluated.

Simulators do not need any temporary variables.

Solution:

What is the difference between 'wire' and 'reg' data types in Verilog?

There is no difference between them

Both 'wire' & 'reg' data types are used for continuous assignment

Both 'wire' & 'reg' data types are used for procedural assignment

'wire' is used for continuous assignment & 'reg' is used for procedural assignment

Solution:

Which of the following statement(s) is/are true about parameters in Verilog?

Verilog allows constants to be defined in a module by the keyword 'parameter'.

Parameters cannot be used as variables.

Parameter values for each module instance can be overridden individually at compile time.

Both 1 and 2 are true.

All 1, 2, and 3 are true.

Solution:

What is the order of execution of the following Verilog code?

initial begin

x = 0;

#0 y = 0;

#0 z = 1;

end

All the statements are executed simultaneously.

Order of executed cannot be determined.

x = 0 is executed first, y = 0 and z = 1 are executed last.

x = 0 is executed first, then y = 0 is executed and finally z = 1 is executed.

System-verilog Questions Set 4:

Which of the following are the 'equality' operators in Verilog?

Solution:

In the code given above, the task is used to convert the units of _________.

Solution:

Which type of ROM can be easily erased even when positioned inside the computer?

Solution:

Which of the following cannot be used while implementing a program using tasks and functions?

Solution:

The Verilog code given below describes the function of a D-Latch using behavioral description.

Solution:

Which of the following variable declaration is correct in Verilog?

Given that the variable is a memory “Mem” of size 64x16

Solution:

Which of the following statements about blocking assignment statements is false?

Solution:

What is the difference between 'wire' and 'reg' data types in Verilog?

Solution:

Which of the following statement(s) is/are true about parameters in Verilog?

Solution:

What is the order of execution of the following Verilog code?

initial begin

x = 0;

#0 y = 0;

#0 z = 1;

end

Solution:

Related Question Sets:

Related Topics:

System-verilog Questions Set 4:

Which of the following are the 'equality' operators in Verilog?

Solution:

In the code given above, the task is used to convert the units of _________.

Solution:

Which type of ROM can be easily erased even when positioned inside the computer?

Solution:

Which of the following cannot be used while implementing a program using tasks and functions?

Solution:

The Verilog code given below describes the function of a D-Latch using behavioral description.

Solution:

Which of the following variable declaration is correct in Verilog? Given that the variable is a memory “Mem” of size 64x16

Solution:

Which of the following statements about blocking assignment statements is false?

Solution:

What is the difference between 'wire' and 'reg' data types in Verilog?

Solution:

Which of the following statement(s) is/are true about parameters in Verilog?

Solution:

What is the order of execution of the following Verilog code? initial begin x = 0; #0 y = 0; #0 z = 1; end

Solution:

Related Question Sets:

Related Topics:

Which of the following variable declaration is correct in Verilog?

Given that the variable is a memory “Mem” of size 64x16

What is the order of execution of the following Verilog code?

initial begin

x = 0;

#0 y = 0;

#0 z = 1;

end