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System-verilog Questions Set 6:

Quiz Mode

If X = 8'b10101101.

Find ^X.

Solution:

What are the results of -7 % 2 and 7 % -2 in Verilog?

-1, -1

-1, 1

1, -1

1, 1

Solution:

`assign out = a ? (b ? i3 : i2) : (b ? i1 : i0)`

What will be the value of "out" when a = 0 and b = 1?

Solution:

Which type of shift operator does the following represent?
"<<<"

Right shift

Left Shift

Arithmetic Right Shift

Arithmetic Left Shift

Solution:

___ are used to connect between hardware entities like logic gates and hence do not store any value on their own.

integers

reg

nets

real

Solution:

Which of the following is the correct way to model 1KB memory in Verilog?

reg mem_1[0:1023];

reg [7:0] mem_2[0:1023];

Both 1 and 2

It is not possible to create 1KB in Verilog

Solution:

Which of the following variable declarations is correct in Verilog?

Given that the variable is a 16-bit net called "Sum"

wire [15:0] sum;

net Sum[15:0];

wire [15:0] Sum;

wire [16:0] sum;

Solution:

Why is coverage important in constrained random verification?

It helps in debugging failures during simulation

It helps in making sure that design specifications are never violated during simulation

It helps in measuring quality of constrained random stimulus used to verify design

None of the above

Solution:

Which of the following statements about static methods is not true?

Static methods can be called outside the class without class instantiation.

Static methods have no access to non-static members and doing so will result in a compiler error.

Static methods can be virtual.

Static methods can be used without creating an object of that type.

Solution:

Which of the following statements about Verilog's `always_comb` and `always` blocks is not true?

All the statements are true.

The always_comb procedure executes automatically at time zero.

The always_comb procedure allows multiple processes to write to the same variable.

The always block can be used to realize both combinational and sequential elements.

Solution:

Related Topics:

Microcontrollers Questions Set 1

Electromagnetic-theory Questions Set 1

Microprocessor Questions Set 1

Control-systems Questions Set 1

Signals-and-systems Questions Set 1

Vhdl Questions Set 1

Analog-designs Questions Set 1

Digital-electronics Questions Set 1

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System-verilog Questions Set 6:

If X = 8'b10101101. Find ^X.

Solution:

What are the results of -7 % 2 and 7 % -2 in Verilog?

Solution:

assign out = a ? (b ? i3 : i2) : (b ? i1 : i0) What will be the value of "out" when a = 0 and b = 1?

Solution:

Which type of shift operator does the following represent?"<<<"

Solution:

___ are used to connect between hardware entities like logic gates and hence do not store any value on their own.

Solution:

Which of the following is the correct way to model 1KB memory in Verilog?

Solution:

Which of the following variable declarations is correct in Verilog? Given that the variable is a 16-bit net called "Sum"

Solution:

Why is coverage important in constrained random verification?

Solution:

Which of the following statements about static methods is not true?

Solution:

Which of the following statements about Verilog's always_comb and always blocks is not true?

Solution:

Related Question Sets:

Related Topics:

If X = 8'b10101101.

Find ^X.

`assign out = a ? (b ? i3 : i2) : (b ? i1 : i0)`

What will be the value of "out" when a = 0 and b = 1?

Which type of shift operator does the following represent?
"<<<"

Which of the following variable declarations is correct in Verilog?

Given that the variable is a 16-bit net called "Sum"

Which of the following statements about Verilog's `always_comb` and `always` blocks is not true?