Which one of the following is a generate block allowed to contain?

wire [1:0]out;

wire [1:0]a = 2'b0x;

wire [1:0]b = 2'bzz;

and (out,a,b);

The value of out is,

Which of the following options correctly represents a 16-bit hexadecimal number in SystemVerilog?

What do the following Verilog gate primitives declare?

bufif0(out, in, ctrl);
bufif1(out, in, ctrl);

Which level of abstraction in digital circuit design makes use of functions that help define the working of the circuit instead of its gate structure?

Which type of coverage is automatically generated by a simulation tool without any extra coding?

What does VHDL stand for?

Which of the following is true about the 'always' block in Verilog Programming?

$display("\"System Verilog\", is a\thardware description and verification language\\")

The output is:

What is the output of the following Verilog code?

typedef enum{APPLE[3], MANGO[2:5] = 4}fruits;

initial begin

fruits f_set_1;

fruits f_set_2;

f_set_1 = APPLE2;

f_set_2 = MANGO4;

$display("value_1 = %0d, name_1 = %s",f_set_1,f_set_1.name());

$display("value_2 = %0d, name_2 = %s",f_set_2,f_set_2.name());

end

endmodule