In VHDL, which symbol is used for assignment of variables/signals?

In the VHDL package "STD_LOGIC_1164", how many types of std_logic values are present?

Which of the following is NOT a type of Wait statement in VHDL?

In which part of the VHDL code are generics declared?

Which of the following predefined keywords are used to define a constant in VHDL?

Which of the following types of statements execute faster?

Which of the following is not a back-end EDA (Electronic Design Automation) tool?

In the VHDL signal assignment statement, which delay model is used in the example x <= 1 AFTER 10ns?

Which of the following is a characteristic of VHDL? 

Which of the following is defined in structural modeling?