ASIC Engineer | RTL Design, Verilog, System Verilog | CDC, Lint | Exp - 4 to 7 years | Bangalore

Overview

Technical leader role on the Cisco SiliconOne team, developing complex ASICs for Enterprise and Service Provider solutions, with ASIC design background and hands-on RTL design experience across the full ASIC/SoC development cycle.

What you'll do

• Understand the architecture in depth, and identify problems and solutions.
• Work across all aspects of implementation: specification, design, timing analysis, power optimization, and flow automation.
• Optimize logic for low power and area, and highlight issues and standard methodologies for power and area optimization.
• Document and improve standard methodologies to make the product successful.

What you'll need

• BS/MS with 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC RTL development.
• Experience with Verilog, SystemVerilog, VCS, Spyglass, CDC, and formal verification.
• Experienced in system debug, SW/HW bring-up, and system validation of silicon towards FCS.
• Gate-level understanding of RTL and synthesis.
• Programming/scripting skills in C, C++, and Perl.
• Hardware emulation platforms and tools, such as EVE and Veloce.
• Good written/verbal interpersonal skills and leadership skills.

Nice to have

• Worked in architecture and definition of high-scale, high-performance ASICs.
• Validated experience in implementation: specification, RTL design, lint, CDC, timing analysis, formal verification, and system testing.
• Validated experience in flow automation (scripting, Makefiles, etc.) and establishing guidelines for the team.
• Good interpersonal skills and validated leadership to accurately describe issues/improvements and lead team for on-time completion.

Details

• Location: Bangalore, India.