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ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)

Qualcomm
NewPosted today

LOCATION

Bangalore · Onsite

EXPERIENCE

Any experience

SKILLS REQUIRED

VerilogClock Domain CrossingLow power designLogic SynthesisEquivalence checkingFormal Verification

Job description

Overview

Work on system power management IP cores and subsystem design for Snapdragon SoCs targeting mobile, compute, IoT and Automotive markets.

What you'll do

  • Carry out micro-architecture and RTL design for IP cores and subsystems.
  • Work in close coordination with Systems, Verification, SoC, SW, PD and DFT teams for design convergence.
  • Enable SW teams to use HW blocks.
  • Qualify designs using static tool checks including Lint, CDC, CLP etc.
  • Run synthesis, LEC and Netlist CLP and report status and progress against expectations.

Nice to have

  • 3 to 8 years of strong experience in RTL design for ASICs.
  • Expertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains.
  • Familiar with UPF and power domain crossing.
  • Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP.
  • Familiarity with bus protocols like AHB, AXI, SPMI, I2C, SPI.
  • Experience in low power design methodology and clock domain crossing designs.
  • Experience in Spyglass Lint/CDC checks and waiver creation.
  • Experience in formal verification with Cadence LEC.
  • Understanding of full RTL to GDS flow to interact with DFT and PD teams.
  • Expertise in Perl/TCL/Python.
  • Experienced in database management flows with Clearcase/Clearquest.
  • Expertise in post-Si debug is a plus.
  • Excellent oral and written communication skills to ensure effective interaction with Engineering Management and team members.
  • Team player, self-motivated, able to work with minimal supervision.

What you'll need

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Details

  • Location: Bangalore, India.

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ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)