ASIC Verification Engineer

Overview

Develop and execute verification for ASIC blocks, cores and SoC designs using SystemVerilog and UVM.

What you'll do

• Develop test plans for all features for Block/Core/SOC and write functional coverage for these features.
• Develop verification environments using SystemVerilog and UVM.
• Architect and develop scalable and re-usable test benches using the framework of the verification methodology.
• Develop BFMs, checkers, monitors and scoreboards.
• Build pseudo-random tests to verify and achieve full functional coverage.
• Debug regression failures in RTL and gate-level simulations, analyze functional coverage gaps and improve tests to cover the gaps.
• Document verification strategy including test plans, testbench, random tests, etc.

What you'll need

• Bachelor's or Master's degree in electrical engineering or a related degree with 8+ years of relevant experience.
• Proficiency in SystemVerilog and verification methodologies such as UVM/VMM/OVM.
• Good command of object-oriented programming principles.
• Knowledge of AMBA AXI/AHB/APB protocols.
• Experience writing functional coverage and pseudo-random tests.
• Flexibility to work in any IP/Subsystem/SoC projects.
• Capability to work independently and deliver.

Nice to have

• Knowledge of host interface protocols such as PCIe, SAS, SATA.

Details

• Location: Pune, India (EON Kharadi Infrastructure).