Chip Power Estimation Engineer

Overview

Develop and improve architectural power estimation models and tools for NVIDIA chips and SoCs, supporting power, performance, and technology decisions.

What you'll do

• Develop and correlate power estimation models and tools.
• Architect power models for use cases, idle power, and I/O power.
• Design model-based tools, testing methods, and infrastructures.
• Calibrate models using measured silicon data.
• Analyze chip configurations and process technology options for power and performance.
• Contribute to performance-per-watt improvements for GPUs and SoCs.
• Collaborate with architecture, design, synthesis, timing, circuit, and post-silicon teams.

What you'll need

• B.Tech. or M.Tech. qualification.
• At least 1 year of experience in power or performance estimation and optimization.
• Strong fundamentals in transistor-level leakage and dynamic power characteristics of VLSI circuits.
• Familiarity with multi-VT, clock gating, power gating, and DVFS.
• Strong background in power estimation techniques, flows, and algorithms.
• Programming skills, preferably in Python.
• Object-oriented programming and design skills.

Nice to have

• Exposure to lab setups and power measurement equipment such as oscilloscopes or DAQs.
• Ability to analyze board-level power issues.
• Exposure to PTPX or EPS power analysis EDA tools.
• Good communication and teamwork skills.

Details

• Location: Bengaluru, Karnataka, India.