DDR Design Verification Sr Lead Engineer

Overview

Senior Lead engineer role focused on DDR subsystem design verification in Qualcomm’s Infra IP team.

What you'll do

• Create DV infrastructure for DDR verification.
• Integrate VIPs for verification.
• Create and execute test plans.
• Debug failures, write assertions, and close functional coverage.
• Ensure high-quality verification deliverables.
• Work with stakeholders to support program success.

What you'll need

• 5+ years of hardware engineering experience or related work experience.
• Bachelor’s degree in Engineering, Electronics, Information Systems, Computer Science, or related field.
• Strong debugging skills.
• UVM and SystemVerilog experience.
• Ability to understand specs/standards and develop test plans.
• Experience building verification components such as monitors, scoreboards, sequencers, and sequences using SystemVerilog/UVM.

Nice to have

• 5+ years of industry experience with digital design concepts.
• Good understanding of DV methodologies and tools.
• Good understanding of LPDDR4/LPDDR5 protocols.
• Good understanding of bus protocols like AHB/AXI/ACE/ACE-Lite.

Details

• Location: Bangalore, India.