Sr Staff Engineer, Design Verification

Overview

Lead digital and mixed-signal SoC verification by building SystemVerilog UVM infrastructure, creating test benches, and driving simulation, coverage, and silicon debug activities.

What you'll do

• Code simulation infrastructure using SystemVerilog (UVM) and C/(ARM,RISC-V Assembly).
• Participate across product development, from specification and circuit modeling through verification and silicon debug.
• Set up a UVM verification environment and develop/verify self-tested test benches for mixed-signal chips and sub-circuits.
• Use and develop advanced UVM and mixed-signal simulation techniques to improve simulation efficiency.
• Generate a verification plan from specifications using vManager and determine coverage/design completeness requirements.
• Create random-constraint tests to cover customer-use-models and build assertions, cover-groups, checkers, monitors, and automatic reporting.
• Set up and run regression reports.

What you'll need

• 10+ years of professional industry experience in digital multi-core SoC verification.
• BSEE (MSEE preferred) or equivalent.
• Experience in digital verification.
• Ability to work independently with limited supervision and collaborate closely with a team.
• Must work from office.
• Proficiency in scripting (Shell, Perl, Python, etc.) and knowledge of Cadence SKILL (plus).
• Experience with RN (Real Number)/digital top-level modeling and verification methodology to speed up simulation (including accuracy/speed tradeoff and interfaces).