Senior Chip Design Verification Engineer

Overview

Senior Chip Design Verification Engineer to own end-to-end unit-level verification of complex chip blocks, covering planning through coverage closure and validating functional and micro-architectural requirements.

What you'll do

• Own end-to-end unit-level (UL) verification from verification planning through coverage closure.
• Collaborate with architecture and micro-architecture teams to review specifications and identify gaps and corner cases.
• Develop verification strategies, environments, checkers, assertions, and coverage for functional and micro-architectural validation.
• Drive verification of complex scenarios including feature interactions, error flows, performance-related behavior, and corner cases.

What you'll need

• 5+ years of experience in verification or a similar position.
• B.Sc./M.Sc. in Computer Engineering, Electrical Engineering, or Communication Engineering, or equivalent experience.
• High-level English ability.
• Ability to work as part of a team.
• Validated experience in verification (preferred/standing out).
• Experience in Specman (preferred/standing out).
• Background in UVM/SV and knowledge in HDL (Verilog/VHDL) (preferred/standing out).