DDR PHY Senior Lead Digital Design Engineer

Overview

Design and develop digital components of high-performance DDR PHY solutions for LPDDR/DDR memory interfaces used in leading-edge SoC products. The role covers architecture, RTL implementation, verification support, synthesis, low-power design, DFT, and silicon bring-up.

What you'll do

• Design and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces.
• Participate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs.
• Drive RTL quality and signoff through lint, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power, and design rule checks.
• Collaborate with the functional verification team to develop verification plans, review coverage closure, and debug design issues.
• Develop synthesis and timing constraints, analyze timing reports, and deliver high-quality netlists for physical design implementation.
• Create and maintain UPF-based low-power intent and perform equivalence checking and low-power signoff.
• Implement and validate Design-for-Test (DFT) features, support scan insertion and ATPG generation, and optimize stuck-at and transition fault coverage.
• Work closely with physical design, STA, DFT, verification, and SoC integration teams to achieve project milestones and quality targets.
• Support pre-silicon and post-silicon bring-up, characterization, debug, and issue resolution across multiple product programs.
• Contribute to methodology improvements, automation, and design flow enhancements to improve engineering productivity and quality.

What you'll need

• B.Tech/M.Tech in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 5+ years of experience in digital design and front-end implementation of complex ASIC/SoC/IP designs.
• Strong understanding of digital design fundamentals, RTL development using Verilog/SystemVerilog, and micro-architecture concepts.
• Hands-on experience with front-end design flows, including lint, CDC/RDC, low-power verification, synthesis, Static Timing Analysis (STA), and Design-for-Test (DFT).
• Familiarity with industry-standard EDA tools used for RTL design, verification, synthesis, and timing closure.
• Strong debugging and problem-solving skills.
• Excellent teamwork, communication, and collaboration skills with global engineering teams.
• A Bachelor's degree in Science, Engineering, or a related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, or a Master's degree in Science, Engineering, or a related field and 2+ years of such experience, or a PhD in Science, Engineering, or a related field and 1+ year of such experience.

Nice to have

• Experience in DDR/LPDDR PHY, high-speed interface, or mixed-signal IP development.
• Knowledge of UPF, power-aware design methodologies, and low-power architecture techniques.
• Familiarity with scan insertion, ATPG, and silicon debug activities.
• Exposure to post-silicon bring-up, validation, and characterization.
• Experience working across multifunctional teams, including verification, physical design, DFT, firmware, and system engineering.

Details

• Location: Bangalore, India.
• Work includes LPDDR5/LPDDR6 and future-generation memory PHY solutions.
• Work includes high-performance, low-power digital architectures for mobile, compute, XR, automotive, and AI platforms.
• Work spans RTL design through silicon validation.