Senior Engineer - AMS IP Verification

Overview

Senior Engineer role focused on AMS IP verification for pre-silicon memory designs. You will build and run simulations and regressions to improve functional coverage for DRAM and emerging memory architectures.

What you'll do

• Provide verification support by simulating, analyzing, and debugging pre-silicon IP designs.
• Develop test cases/stimulus to increase functional coverage for DRAM and emerging memory architectures.
• Develop and maintain test benches and test vectors using simulation tools, running regressions for coverage analysis.
• Co-work with international colleagues to develop new verification flows for DRAM and emerging memory designs.
• Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.

What you'll need

• 2+ years of experience in AMS/Mixed Signal design verification.
• Good understanding of analog/mixed signal circuits.
• Experience in analog and mixed signal verification and tools including Virtuoso, primesim/Finseim, Hspice, Xcellium, Simvision, and Waveview.
• Hands-on experience writing Verilog models, including Verilog A/MS and RVM model writing (encouraged).
• Hands-on experience building SPICE testbenches at Block and Fullchip level.
• Hands-on experience with SV/UVM-based verification and SV/PSL assertions.
• Good scripting skills using Perl and Python (highly encouraged).
• Good communication and debugging skills, and ability to work well in a team.

Details

• Location: Bengaluru, Karnataka, India.