Design Engineer II

Overview

Design Engineer II responsible for developing verification infrastructure and applying advanced verification methods to processor-related designs.

What you'll do

• Develop simulation testbenches in C, C++, and RTL.
• Lead development of reusable UVM environments.
• Integrate formal verification into verification workflows.
• Apply AI-driven coverage analysis.
• Partner with microarchitecture, RTL design, and software teams on verification plans.
• Align verification plans with ISA requirements.

What you'll need

• B.Tech or M.Tech in ECE.
• Experience with SystemVerilog and UVM.
• Experience with C/C++ for architectural modeling.
• Experience with processor integration, such as RISC-V or ARM.
• Experience with AMBA or PCIe protocols.
• Expertise in Perl, Python, or Tcl scripting for verification automation.
• Experience verifying complex pipelines, memory subsystems, or ISA implementations.

Details

• Location: Noida, India.