Design Verification Engineer

Overview

Design Verification Engineer for an ASIC Verification team, focused on reliable and functional validation of advanced digital designs.

What you'll do

• Drive test planning for ASIC projects.
• Develop robust test benches to support cutting-edge ASIC work.
• Collaborate with design, design-verification, and physical design teams to integrate and validate test logic.
• Identify and resolve technical issues using debugging tools and scripting.
• Develop and refine verification strategies to improve coverage and efficiency.

What you'll need

• 2+ years of experience in design verification.
• Bachelor’s or Master’s degree in Electrical or Computer Engineering or a related field.
• Experience in test planning based on complex design specifications.
• System Verilog testbench development experience.
• Hands-on debugging experience, preferably with DVE and Verdi.
• Scripting proficiency in at least one of Tcl, Python, or Perl.

Nice to have

• Knowledge of UVM and System Verilog.
• Experience adapting verification strategies for AI calibration and emerging technologies.

Details

• Hybrid work: four days per week at Cisco’s Yerevan office.