Engineer IP Verification - Digital Design Verification

Overview

Engineer for IP and digital RTL verification, responsible for defining verification scope and executing block/chip RTL verification using simulation-based methods.

What you'll do

• Define verification scope, strategy, and plans based on design specifications.
• Develop and maintain verification testbenches and test vectors using SV-UVM.
• Run directed and constrained-random tests and regression suites and triage failures.
• Close functional/code coverage and identify verification holes to support tapeout readiness.
• Simulate, analyze, and debug block-level RTL, testbench, and environment issues.
• Develop test cases/stimulus to improve functional coverage for DRAM architectures and features.
• Provide verification status and communicate risks to stakeholders.

What you'll need

• 2-3 years of experience with a Bachelor’s degree, or a Post Graduate Degree in Electronics Engineering or related engineering.
• Good knowledge of digital circuits and RTL verification concepts.
• Working knowledge of tools including Virtuoso, Xcellium, Simvision, and Verdi/Verisium.
• Knowledge of SV and UVM-based verification testbenches at block level.
• Scripting skills using Perl or Python (Perl/Python is a plus/requirement noted as “is a plus”).
• Ability to proactively adopt approved AI tools to support verification workflows and scripting.

Details

• Co-work with international colleagues on developing new verification flows.