FPGA Silicon Design Verification Engineer

Overview

FPGA Silicon Design Verification Engineer for pre-silicon verification of FPGA IP blocks, subsystems, and SoC-level designs.

What you'll do

• Develop and execute verification plans from architecture and design specifications.
• Build and maintain reusable SystemVerilog/UVM verification environments, testbenches, sequences, and scoreboards.
• Create directed and constrained-random tests to verify FPGA designs.
• Define and track verification metrics such as functional coverage, code coverage, and assertion coverage.
• Develop SystemVerilog Assertions (SVA) for design validation and corner-case detection.
• Debug failures and perform root-cause analysis using simulation, emulation, waveform analysis, and protocol analyzers.
• Drive verification closure and ensure quality signoff before tape-out or FPGA release.

What you'll need

• 3+ years of digital design verification experience for FPGA or ASIC products.
• SystemVerilog with UVM (Universal Verification Methodology) experience.
• Assertion-based verification (ABV) skills.
• Constrained-random verification methodology knowledge.
• Digital design fundamentals including CDC, reset synchronization, pipelines, state machines, and memory architectures.
• Experience with simulators including Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, or similar.
• Scripting proficiency in Python, Perl, Tcl, or Shell and version control experience using Git.

Details

• Job type: Regular.
• Shift: Shift 1 (Malaysia).
• Primary location: Penang 15, Penang, Malaysia.