Senior Design Verification Engineer

Overview

Senior Design Verification Engineer for ASIC functional verification on Cisco Silicon One chips, supporting verification from pre-silicon through post-silicon validation activities.

What you'll do

• Implement DV infrastructure for block, cluster, and TOP-level environments.
• Maintain existing DV environments and enhance them.
• Ensure complete verification coverage through code and functional coverage implementation and review.
• Work with architects and designers to achieve verification completeness.
• Support tests performed with emulation.
• Contribute to tasks preparing for post-silicon-validation.

What you'll need

• 5+ years of experience in digital logic design verification.
• Advanced knowledge of SystemVerilog.
• Advanced knowledge of UVM.
• Advanced debug skills pre-silicon and in-lab.

Nice to have

• Scripting abilities.
• System integration knowledge: AMBA, PCIe, SPI, I2C, JTAG, CPU.
• Basic SW knowledge (chop driver level).
• Basic design knowledge.

Details

• Based in Serbia.