DFT ASIC Engineering Technical Leader | ATPG | 10 to 14 years | Bangalore

Overview

Lead DFT engineering for next-generation silicon designs, overseeing test feature development and improving yield, reliability, and manufacturability.

What you'll do

• Lead, mentor, and develop a team of DFT engineers.
• Design and implement DFT features for high-quality, testable, manufacturable silicon.
• Drive DFT execution across the product lifecycle from pre-silicon to production qualification.
• Collaborate with chip architects, design, and verification teams to define and standardize DFT strategies.
• Supervise ATPG, scan compression, memory BIST, and other advanced DFT techniques to improve coverage and efficiency.
• Guide debugging and root-cause analysis of silicon failures to improve yield and reliability.
• Establish and continuously improve DFT methodologies and best practices.

What you'll need

• BTech/Mtech in Electrical/Computer Engineering or related field.
• 10+ years of demonstrated experience.
• Hands-on experience with DFT features such as scan insertion, BIST, or boundary scan.
• Experience leading and developing engineering teams (mentoring, performance management, project planning).
• Proficiency across the product lifecycle from pre-silicon design to silicon bring-up and production qualification.

Details

• Job title: DFT ASIC Engineering Technical Leader | ATPG.
• Location: Bangalore.