Senior Staff Engineer

Overview

Senior Staff Engineer role focused on developing and deploying Design-for-Test (DFT) solutions for complex SoC/ASIC products.

What you'll do

• Develop and implement DFT architectures and methodologies for complex SoCs.
• Integrate DFT features into the chip design flow with Design, Verification, and Backend teams.
• Create, execute, and validate test strategies for high fault coverage and reliable defect detection.
• Perform scan insertion and DFT DRC analysis, including issue resolution.
• Drive ATPG, MBIST, and IJTAG implementation, validation, and sign-off.
• Support silicon bring-up, characterization, and debug for product ramp-up.
• Develop and maintain automation scripts to improve DFT flow efficiency and scalability.

What you'll need

• 6 to 9+ years of hands-on experience in DFT and ASIC/SoC design and implementation.
• Strong understanding of digital design fundamentals, RTL concepts, simulation methodologies, and test architectures.
• Expertise in scan architecture, scan insertion, DFT DRC closure, and boundary scan (JTAG) implementation and debug.
• Proficiency in ATPG generation, fault coverage analysis, MBIST insertion, and verification and debug.
• Experience in IJTAG integration, verification, and sign-off activities.
• Hands-on experience with Siemens Tessent, Synopsys TetraMAX, and Cadence Genus DFT tools.
• Programming/scripting skills in Perl, TCL, and Python; and ability to use Verilog/VHDL.

Details

• Location: Bangalore.