Senior Circuit Silicon Correlation DFT Engineer

Overview

Senior Circuit Silicon Correlation DFT Engineer to help design, debug, and correlate silicon behavior with pre-silicon performance and power models, including RAM correlation and DFT methodology development.

What you'll do

• Participate in processor design and debug in deep submicron technologies.
• Generate ATPG patterns for silicon speed path debug.
• Perform RTL and gate-level verification for ATPG and non-ATPG patterns.
• Correlate diagnosis results to real design failures.
• Develop RAM correlation by studying RAM circuit failure mechanisms and limits on silicon.
• Create new DFT infrastructure methodologies to analyze mis-correlation in logic and around RAM.

What you'll need

• Have a BSEE required and/or MS preferred in Electrical or Electronics Engineering.
• Have 8+ years of experience.
• Demonstrate solid understanding of DFT, including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
• Understand DFT and logic design.
• Bring up RTL/gate-level simulation, write testcases, and debug them.
• Have scripting proficiency in at least one of Python, Perl, Tcl, or Make, plus automation methods/algorithms.
• Have experience with pattern generation using tools such as Tessent.

Details

• Work mode: Hybrid (#LI-Hybrid).