Staff Engineer

Overview

Staff Engineer role focused on RTL, verification, and DFT for complex memory, IO subsystems, and hierarchical digital blocks, including BIST.

What you'll do

• Develop RTL for digital and memory subsystems.
• Verify digital subsystems and memory BIST implementations.
• Perform MBIST, ATPG, RSQ verification, and DFT sign-off.
• Conduct formal verification and cross-clock-domain checks.
• Support power and timing sign-off.
• Verify complex digital subsystems using OVM and UVM methodologies.
• Create verification suites independently.

What you'll need

• Hands-on experience with RTL and synthesis.
• Experience defining ICC and synthesis constraints for timing closure.
• Familiarity with MBIST, ATPG, RSQ, and DFT sign-off methodologies.
• Familiarity with SpyGlass, LEC, CDC, and synthesis tools.
• Proficiency with Verilog NC and Verilog XL tools.
• Strong fundamentals in digital design and complex RTL coding and verification.

Nice to have

• Familiarity with GLS, simulation, UVM, and OVM methodologies.

Details

• Location: Bangalore Electronic City, India.