Staff DFT Engineer

Overview

Staff DFT Engineer role focused on defining and implementing DFT strategy and verification, with expertise across IJTAG/SSN/ATPG and IC-level DFT work for mixed-signal designs.

What you'll do

• Define DFT strategy and requirement specifications for DFT verification using gate-level and timing simulations.
• Work with design teams to define and implement DFT.
• Debug DFT issues including simulation failures, ATPG coverage gaps, and DRC improvements.
• Collaborate with STA engineers to define timing constraints for DFT modes.
• Work with layout engineers to ensure DFT logic is implemented correctly.
• Support test engineering in silicon debug and pattern delivery for ATE.

What you'll need

• Strong knowledge and experience in scan insertion, compression, ATPG, memory BIST, and JTAG at IC level for mixed-signal designs.
• Expert experience in IJTAG, SSN, and ATPG verification.
• Experience with Mentor DfT tools and Synopsys DC and simulator tools.
• Hands-on experience with Primetime.
• Experience in RTL coding and shell/Perl scripting.
• Knowledge of SystemVerilog interfaces and lint checks (preferred).