Display Synthesis Engineer, Sr Lead

Overview

Senior Lead Display Synthesis Engineer role focused on implementation for the Display Sub-System, including synthesis, low-power constraint development, and timing/quality execution across complex multi-clock designs.

What you'll do

• Lead synthesis and signoff-quality constraint development for display subsystem implementation.
• Develop and validate power intent constraints, including UPF-related work.
• Run and analyze RTL lint/LEC/Low Power checks and handle Memory BIST insertion and execution.
• Develop and update TCL scripts for synthesis/analysis and debugging.
• Perform hands-on work with Synopsys DCG/Genus/Fusion Compiler and Synopsys PrimeTime.
• Execute timing closure activities for multi-clock domain designs and support netlist/timing constraint validation.

What you'll need

• Have 3+ years of hardware engineering or related work experience (or 5+ years per degree requirement section).
• Experience in synthesis, LEC, and low-power checks.
• Experience with Memory BIST insertion and constraints validation.
• Ability to write timing constraints for synthesis and STA and support timing closure/pipelining.
• Familiarity with MCMM synthesis and optimization.
• Scripting experience with Perl/Python and TCL.

Details

• Location: Bangalore, India.