Principal Engineer Design

Overview

Principal Engineer Design to lead physical implementation and timing closure for advanced low-power SoCs for IoT and MCU markets.

What you'll do

• Lead physical design and timing closure for complex low-power SoCs for IoT/MCU applications.
• Manage end-to-end physical implementation from floor planning through final signoff to meet PPA objectives.
• Optimize die area, timing, power, and performance for hierarchical block-level and full-chip designs.
• Own package co-design, power planning, power grid design, place-and-route, CTS, timing closure, and physical signoff activities.
• Ensure timing convergence across multiple operating modes and PVT corners.
• Oversee physical verification, signoff validation, and design readiness reviews.
• Collaborate with cross-functional teams to resolve implementation challenges and drive EDA/methodology improvements.

What you'll need

• 8+ years of hands-on experience in Physical Design and Timing Closure for complex SoC products.
• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or related discipline.
• Proven success driving chip implementation from floor planning through tape out and silicon delivery.
• Deep expertise in hierarchical SoC physical design, implementation, and timing convergence.
• Strong proficiency with industry-standard Physical Design, Signoff, and EDA automation tools.
• Hands-on experience with floor planning, power planning/power grid design, P&R, CTS, and STA (including MMMC timing closure).
• Experience with physical verification and signoff including EM/IR and power integrity analysis.

Details

• Location: Bangalore BTP.