Lead Logic Design for UALink IP/Subsystem Engineer

Overview

Lead RTL and microarchitecture development for UALink-based IP/subsystems, with focus on high-bandwidth, low-latency interconnect design.

What you'll do

• Lead UALink IP/subsystem RTL development.
• Translate protocol requirements into microarchitecture.
• Design control and data-path logic for high performance.
• Work on buffering, arbitration, flow control, ordering, and error handling.
• Develop and review SystemVerilog RTL.
• Drive performance, area, power, and latency optimization and debug issues.
• Review RTL, mentor engineers, and support silicon debug and issue resolution.

What you'll need

• 6–10 years of experience.
• Strong RTL and microarchitecture experience.
• Experience with high-speed interconnects.
• Strong understanding of data movement, flow control, arbitration, and buffering.
• Excellent SystemVerilog/Verilog skills.
• Experience with CDC, lint, synthesis, and timing.
• Strong debugging and technical leadership skills.

Nice to have

• Direct UALink experience.
• Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
• Experience with AI/accelerator or high-performance compute SoCs.

Details

• Location: Bengaluru, Karnataka, India.