Engineer-std cell layout

Overview

Design and maintain standard-cell layouts for new DRAM products on new technologies, leading projects through specification, verification and PPA-qualified library release.

What you'll do

• Design and maintain standard-cell layouts for new DRAM products on new technology.
• Lead standard-cell layout projects from initial specification definition through PPA-qualified library release.
• Collaborate with the DTCO team to develop standard-cell architecture for emerging technologies.
• Perform layout verification, including LVS, DRC and latchup, as well as quality checks and documentation.
• Deliver block-level layouts on time with acceptable quality.
• Plan, estimate area and time, schedule, delegate and execute work to meet project schedules and milestones in a multiple-project environment.
• Guide junior team members in executing sub-block-level layouts and review their work.
• Contribute to effective project management.
• Develop new flows and methodologies to reduce standard-cell manual effort and increase productivity.
• Work with the Process team, CMOS and CAD to negotiate DRC for new technology.
• Co-work with international colleagues to develop new flows and tools for standard-cell layout and design.
• Leverage AI tools to automate tools and workflows.
• Use AI-assisted workflows to improve design productivity.

Details

• Location: Hyderabad, India.