Formal Verification Engineer

Overview

Formal Verification Engineer on the Silicon Chassis team, responsible for applying formal methods to verify interconnect fabrics, protocol bridges, and link-layer logic.

What you'll do

• Develop formal verification test plans, scopes, strategies, and methodologies.
• Create abstraction models for complex-design convergence and formal analysis.
• Generate and validate proofs, troubleshoot failing tests, and implement corrective measures.
• Collaborate with architecture, RTL design, and physical implementation teams.
• Maintain formal verification tools, methodologies, and infrastructure.
• Model design verification challenges at the architecture level.
• Document plans, track progress, and lead cross-functional technical reviews.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 4+ years of formal verification experience.
• Alternatively, a relevant master's degree with 3+ years of experience.
• Alternatively, a relevant PhD with no prior professional experience.
• Proficiency in formal verification, model checking, and equivalence checking.
• Strong knowledge of SystemVerilog, Verilog, logic, and microarchitecture fundamentals.
• Experience with abstraction modeling, simulation techniques, and convergence strategies.
• Familiarity with Binary Decision Diagrams and Data Flow Graphs.

Nice to have

• Ability to resolve complex architectural and formal verification challenges.
• Cross-functional collaboration and teamwork experience.
• Technical documentation and communication abilities.
• Interest in improving verification tools and methodologies.

Details

• Location: Bangalore, Karnataka, India.
• Hybrid work model with on-site and off-site work.
• Experienced Hire position.