Formal Verification CAD Engineer

Overview

Formal Verification CAD Engineer responsible for verifying complex design blocks and improving formal verification methodologies and sign-off quality.

What you'll do

• Drive formal verification of complex design blocks using Formal Apps and convergence strategies.
• Collaborate with architecture, design, and systems teams on verification goals.
• Review and refine formal setups, proofs, constraints, and abstractions.
• Engage with EDA vendors to evaluate verification methodologies.
• Develop Python automation scripts for formal verification flows.
• Analyze formal verification problems and propose verification strategies.
• Support low-power formal methodology.

What you'll need

• 2+ years of hands-on formal verification experience.
• Strong understanding of formal concepts, proof strategies, and abstraction techniques.
• Proficiency with formal tools such as Jasper, VC Formal, or Questa Formal.
• Strong scripting skills, with Python preferred.
• Strong analytical, problem-solving, communication, and collaboration skills.
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field.

Nice to have

• Working knowledge of property-based formal verification using SVA.
• Low-power knowledge, including UPF/CPF and power-aware verification concepts.

Details

• Location: Bangalore, India.