Full-Chip Physical Design Verification Engineer

Overview

SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon.

What you'll do

• Lead physical verification closure including DRC, LVS, and ERC.
• Debug issues using standard industry PV tools.
• Drive signoff through complex verification flows.
• Collaborate across RTL, PD, CAD, and packaging to achieve successful tapeouts.
• Ensure manufacturable, high-quality silicon across advanced technology nodes.

What you'll need

• 7–14 years of hands-on CPU/IP/SoC physical verification experience.
• Experience with DRC, LVS, ERC, PERC, Antenna, and DFM verification.
• Proficiency with industry-standard tools and flows including Calibre, ICV, Pegasus, FC, and Innovus.
• Knowledge of ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop and EM).
• Understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
• Scripting proficiency in Python and TCL for automation and flow optimization.
• BS/MS in Electrical/Electronics Engineering (or related).

Details

• Work mode: hybrid.
• Based in Santa Clara, CA; Austin, TX; or Fort Collins, CO.