Infra Design Verification Sr Lead Engineer

Overview

Senior Lead Engineer focused on infra design verification for high-speed interconnect protocols and subsystem components.

What you'll do

• Develop and maintain UVM-based verification environments for PCIe, CXL, AXI.
• Create and execute verification plans for PCIe, CXL, AXI, and CHI.
• Perform block-level and top-level verification with functional coverage, SVA, and regression testing.
• Collaborate with RTL designers, architects, and validation teams to ensure correctness and coverage closure.
• Use third-party VIPs for protocol compliance and simulation.
• Integrate and validate SMMU and Coresight components in subsystem environments.

What you'll need

• 3+ years hardware engineering experience (or 2+ with a master’s, or 1+ with a PhD) in related fields.
• Strong proficiency in SystemVerilog, UVM, and verification methodologies.
• Deep understanding of PCIe Gen3/4/5/6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
• Familiarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.
• Expertise in assertion-based verification (SVA) and coverage-driven testing.
• Proficiency in Perl/Python/Tcl scripting for automation.