Interim Engineering Intern – 2027, HW

Overview

Interim Engineering Intern (HW) focused on SOC and hard macro physical design, including validation/debug, RF/analog layout, and design/verification tasks.

What you'll do

• Support SOC validation and debug activities.
• Work on RF and analog layout for RF/analog/mixed-signal/power IC design.
• Contribute to low power design efforts.
• Participate in board and FPGA design.
• Assist with digital ASIC design and design/SOC verification.
• Work on CAD solution engineering and design for test (DFT).
• Support CPU design activities.

What you'll need

• Experience verifying SoC with embedded RISC/DSP processors and communications/networking ASICs.
• Proficiency with Verilog or VHDL and C/C++.
• Knowledge of Tcl/Perl/shell scripting.
• RTL design experience and/or strong object-oriented (OO) programming knowledge.
• Required RF/analog/mixed-signal IC design knowledge including PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or layout.
• Excellent analytical and problem-solving skills.
• Ability to collaborate in teams and communicate verbally and in writing.

Details

• Location listed as Bangalore, India and Hyderabad, Telangāna, India.
• Role is an Interim Engineering Intern.