Lead Engineer – CAD Digital Verification

Overview

Develop, enhance and support CAD tools and EDA simulation flows that enable efficient and reliable verification of Silicon Labs' semiconductor products, working within the CAD – Digital Simulation team.

What you'll do

• Develop, deploy and maintain CAD tools and EDA flows supporting Design Verification, Formal Verification, Low Power, Functional Safety and Coverage Analysis.
• Work closely with RTL design and verification teams to understand technical requirements, identify challenges and develop solutions that improve engineering productivity.
• Develop and optimize automation scripts using Python, Perl, Tcl, Bash and shell scripting to streamline simulation builds, testbench generation and verification workflows.
• Support ASIC/SoC simulation environments, including RTL simulation, gate-level simulation (GLS) and UVM-based verification flows.
• Collaborate with EDA vendors such as Cadence, Synopsys and Siemens EDA to integrate new capabilities, debug tool issues and resolve simulation bottlenecks.
• Support verification engineers in debugging complex simulation failures, analyzing functional and code coverage and improving verification efficiency.
• Develop reusable and scalable CAD methodologies and automation solutions to improve verification quality and reduce turnaround time.
• Participate in technical discussions, project planning and roadmap reviews, providing regular updates on tool enhancements and deployment activities.

What you'll need

• Bachelor's degree in Electrical Engineering, Electronics, Computer Engineering or a related field with 7+ years of relevant industry experience, or a Master's degree with 5+ years of experience.
• Experience in Design Verification, CAD/EDA tool development or verification flow support for ASIC/SoC designs.
• Strong understanding of IP/SoC-level verification methodologies and digital simulation environments.
• Hands-on programming and automation experience using Python, Perl, Tcl, C/C++, Makefiles or shell scripting.
• Familiarity with RTL, Verilog/SystemVerilog and UVM-based verification environments.
• Experience working with EDA simulation tools and verification workflows.
• Good understanding of Linux/UNIX environments, scripting and engineering data-management workflows.
• Strong debugging, problem-solving, communication and cross-functional collaboration skills.

Nice to have

• Experience with Cadence simulation and verification tools, including Cadence SYSVIP, SYSAPI or SPA.
• Knowledge of low-power verification methodologies, UPF and gate-level simulation (GLS).
• Experience with DPI integration using C/C++ for simulation and debugging.
• Exposure to formal verification, functional safety and advanced coverage methodologies.
• Experience supporting or developing EDA flows using Cadence, Synopsys or Siemens EDA tools.
• Demonstrated ability to debug complex EDA tool issues and collaborate with vendors to resolve technical challenges.
• Experience developing scalable automation frameworks and improving simulation performance across multiple engineering teams.
• Ability to work independently, manage technical priorities and drive solutions in ambiguous or complex engineering environments.
• Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis and decision-making.

Details

• Location: Hyderabad.