Lead Engineer - Design Verification (Low power UPF/CPF)

Overview

Lead Design Verification Engineer focused on low-power design verification for complex SoCs, validating power intent and low-power features using UPF/CPF across the design lifecycle.

What you'll do

• Understand and verify power domains and power intent using UPF/CPF.
• Develop and execute test plans for low-power modes and states.
• Drive functional and assertion coverage closure.
• Build and enhance SystemVerilog/UVM verification environments.
• Perform power-aware verification and debug complex issues.
• Collaborate with cross-functional teams on advanced DV methodologies.

What you'll need

• 6–8 years of experience in design verification.
• BS/MS in Electrical or Computer Engineering (or related field).
• Strong SystemVerilog/UVM skills.
• Experience with assertion-based and coverage-driven verification.
• Solid understanding of low-power design techniques.
• Experience with UPF/CPF-based verification.
• Strong debugging and problem-solving skills.

Nice to have

• Experience with formal/static verification.
• Familiarity with Synopsys NLP tools.
• Scripting skills (Python/Perl).
• Experience with ASIC tools and flows.

Details

• Role involves low-power design verification for complex SoCs.