Senior Manager - SOC Verification

Overview

Senior Manager - SOC Verification responsible for ensuring the functional integrity of next-generation 32-bit dsPIC MCU products.

What you'll do

• Own complex SoC verification strategies for devices with ARM and proprietary cores.
• Perform SOC-level design verification of complex digital macros using architectural descriptions.
• Build a test and testbench environment using VMM/UVM/SystemVerilog.
• Handle RTL and gate-level verification of 16-bit microcontroller products.
• Analyze gate-level simulations and timing violations and coordinate with the STA team.
• Develop functional safety tests, fault injection simulations, and coverage analysis.
• Debug complex full-chip issues and mentor junior team members.

What you'll need

• 10+ years experience in SoC verification.
• Bachelor of Engineering in Electronics/Electrical or Computer Science with strong digital design fundamentals.
• Expert-level command of SystemVerilog and UVM.
• Hands-on experience with Formal Verification (property/ connectivity checking) using JasperGold or VC Formal.
• In-depth knowledge of AMBA bus protocols (AHB, APB, AXI).
• Experience defining coverage-driven verification (CDV) metrics and managing regression suites.
• Domain expertise in MCU peripherals including DMA, timers, ADC/DAC interfaces, security modules, and functional safety.
• Direct experience verifying SoCs with ARM cores (Cortex-M) and proprietary RISC-based architectures.

Details

• Travel time: 0% - 25%.