[EMN] Senior IP Design Verification Engineer

Overview

Senior IP Design Verification Engineer to own silicon IP pre-silicon verification end-to-end, from planning to sign-off.

What you'll do

• Execute silicon IP pre-silicon verifications from planning through verification sign-off.
• Develop, enhance, and maintain verification environments, testbenches, test cases, checkers, and coverage models.
• Run simulations and regressions, analyze failures, and debug issues.
• Drive root-cause resolution with IP, integration, and system teams.
• Track verification progress, report status, highlight risks, and propose mitigation actions.
• Review verification results, ensure process compliance, and participate in technical reviews and discussions.
• Guide junior engineers on verification methodology, debugging approach, and efficient task execution.

What you'll need

• At least 5+ years of experience in design verification.
• Solid knowledge of the ASIC/SoC development lifecycle.
• Hands-on experience with OVM/UVM using SystemVerilog.
• Experience with testbench development/enhancement, test case creation, coding, execution, and regression runs.
• Experience with AXI VIP and AXI protocol verification.
• Strong root-cause analysis and debugging skills across testbench, integration, and IP boundaries.
• Fluency in written and spoken English.

Nice to have

• Hands-on experience with UCIe.

Details

• Bachelor’s degree in Electronics, Electrical Engineering, or a comparable discipline.
• Onsite opportunities: short-term and long-term assignments in worldwide offices.